MRD F2F Decoder Chip / MRD520

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Features

Decoder IC for F2F encoded magnetic stripe
CMOS integrated circuit with built-in operational amplification circuitry
Available for single, dual or triple track decoding solutions
Support 75/210 BPI recording density
Adjustable output clock pulse width 14 to 60 gs.
Ignore start bit selectable for 4 or 8 bits
Idle mode controllable by external hardware or Micro-Processor
Accept magnetic head data input frequency from 300 to 12600 bit/sec
 
Order information

Part Number

Pb free

Temperature Range

Package Type

MRD520A-L

Yes

-10XC to +70XC

28-pin SOP