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MRD520

Magnetic Stripe Frequency/Double Frequency (F2F) Triple Track Decoder Chip

The MRD520 is a 28-pin small outline package (SOP) integrated circuit used for decoding magnetic stripe data. The frequency/double frequency (F2F) decoder integrated circuit is used to recover F2F encoded data received from a magnetic head. It is commonly used in Point-of-Sales terminal and electronic money transfer terminal. It is capable of one, two and three track magnetic stripe reading. The MRD520 accepts magnetic head data input frequency from 300 to 12600 bit/sec.


Overview

Features & Benefits

  • Dual track F2F decoder chip
  • SOP 28 PIN
  • Decoder IC for F2F encoded magnetic stripe
  • CMOS integrated circuit with built-in operational amplification   circuitry
  • Available for single, dual or triple track decoding solutions
  • Support 75/210 BPI recording density
  • Adjustable output clock pulse width 14 to 60 gs
  • Ignore start bit selectable for 4 or 8 bits
  • Idle mode controllable by external hardware or Micro-Processor
  • Accept magnetic head data input frequency from 300 to 12600   bit/sec

Specifications

Certifications

Applications

Banking
Gaming
Vending
Hospitality
Petroleum
Parking
Retail
Transportation
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